Senior Physical Design Engineer -Python / EDA Tools

Senior Silicon Physical Design Engineer-RTL / GDS

Our client is a globally known artificial intelligence chip manufacturer that creates AI hardware and software platforms for edge computing who are looking for a Senior Silicon Physical Design Engineer with extensive expertise in ASIC Physical Design, from RTL to GDS to join their team at their site in Eindhoven.

If this is, you please continue reading below!

Essential Skills

• Experience in Physical Design, including a proven track record of implementing designs from RTL to GDS.
• Your expertise includes synthesis, floor planning, place and route, extraction, timing analysis, and physical verification. You understand constraints generation, STA, timing optimization, and timing closure.
• You have hands-on experience with EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
• You possess a proficient understanding of clock tree synthesis (CTS) and different clock-building techniques.
• You have experience in IP integration, covering memories, IOs, embedded processors, double data rate, networking fabrics, and Analog IP.
• Proficiency in scripting languages such as Python, Tcl, or Perl.

Desirable Experience

• Expertise in chip top-level integration, I/O ring design, ESD, and latch-up methodologies.
• Experience collaborating directly with tool vendors, driving resolution of tool issues and improvements.
• Understanding of semiconductor device physics and transistor characteristics.
• Experience with multi-clock, multi-power-domain design.
• Knowledge of continuous integration methodology and architecting regression test-suites.

What are you waiting for?! Apply via LinkedIn, or send your CV to fm@eu-recruit.com.

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