UVM Verification Engineer

UVM Verification Engineer

Hybrid (2-3 weeks Remote p/month)

A great opportunity for an experienced Verification Engineer to join a global leader in power and sensing solutions, who specialise in the architecture, design and development of advanced technology mixed signal power devices.

Your focus will be to use cutting edge tools to verify state of the art products in our Model Based Design flow for digital signal processing applications

Responsibilities:

• Preparation of digital design test plan from requirements using Cadence-vManager/vPlanner
• Definition and creation of UVM-SV test environment, test plans, tests and functional coverage
• Verification of signal processing and control algorithms using Cadence and MathWorks tools
• Analysis of test results, improving test coverage and debug of unexpected design behaviors
• Running and maintenance of regression runs
• Preparation and/or leading of verification reviews
• Modification and/or debug of Simulink models in mixed signal test environment
• Coordination of verification activities with abroad team members
• Cooperation with System Engineering team on Jama Requirements

Qualifications:

• Bachelor’s / Master’s Degree
• 5+ / 3+ years of experience in Digital Design and/or Verification.
• Excellent communication, documentation, problem-solving and analytical skills are required.
• Knowledge of SystemVerilog and UVM is a must.
• Experience with the usage of Jama, MATLAB/Simulink, Python is a strong plus.

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