UVM Verification Engineer (Hybrid)

UVM Verification Engineer

A fantastic opportunity for an experienced Digital Verification Engineer to join a global leader in Power and Sensing Semiconductor Solutions alongside their team in Milan, Italy.

**(Option to work 2-3 weeks p/month Remotely.)**

In this position your primary focus will be using cutting edge tools to verify state of the art products in our Model Based Design flow for digital signal processing applications. As a member of product development team, you will also be exposed to variety of tools including MathWorks Simulink, embedded microprocessor coding, MATLAB scripting and Jama Requirements Management.

Your role

• Preparation of digital design test plan from requirements using Cadence-vManager/vPlanner
• Definition and creation of UVM-SV test environment, test plans, tests and functional coverage
• Verification of signal processing and control algorithms using Cadence and MathWorks tools
• Analysis of test results, improving test coverage and debug of unexpected design behaviour
• Running and maintenance of regression runs
• Preparation and/or leading of verification reviews
• Modification and/or debug of Simulink models in mixed signal test environment
• Coordination of verification activities with abroad team members
• Cooperation with System Engineering team on Jama Requirements

Your profile

• Bachelor’s / Master’s degree of 5+ / 3+ years of experience in Digital Design and/or Verification.
• Excellent communication, documentation, problem-solving and analytical skills are required.
• Knowledge of System Verilog and UVM is a must.
• Experience with the usage of Jama, MATLAB/Simulink, Python is a strong plus.

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