Verification Engineer – Contract – UVM / SystemVerilog

Verification Engineer – Contract – UVM / SystemVerilog

  • Permanent, Full Time
  • Cambridge, UK
  • Applications have closed

Website European Recruitment

Looking for your next contract in Verification?

Does the likes of Cambridge appeal to you?

Verification Engineer – Contract

European Recruitment are looking for a Verification Engineer who can start immediately to join one of the worlds leading Semiconductor companies in Cambridge. The main function of the role will be to plan, design and develop UVM block level test benches for products.

About you:

  • Extensive experience architecting/implementing verification test benches for complex IP/module designs using structured and maintainable strategies
  • Expert Knowledge of SystemVerilog and UVM methodologies
  • Experience of applying constrained random, coverage driven and assertion-based verification techniques coupled with an in-depth understanding of object-oriented methodologies
  • Video, CPU, GPU or display verification experience is a big plus


This is a hot new contract looking for some to take their next step in contracting with one of the largest Semiconductor companies. The start date would be preferably be around the start of December.

Please note that there will be no Visa sponsorship available.

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