Verification Engineer (UVM) – Cambridge, UK

Principal Verification Engineer (UVM) – on-site – Cambridge, UK

Relocation Assistance provided

Responsibilities:

Experienced Verification Engineers needed for all phases of CPU project verification:

• Own specific CPU project areas, from testbench development to verification methodology.

• Produce test plans and strategies.

• Coordinate tasks to ensure high-quality, timely results.

• Maintain verification standards.

• Contribute to verification improvement strategies.

• Identify causes of issues throughout verification process.

Required Skills:

• Design and implement verification environments for complex RTL designs.

• Proficient in hardware verification languages like SystemVerilog or Specman ‘e’.

• Understand end-to-end verification processes.

• Grasp complex specifications quickly.

• Familiarity with computer architecture fundamentals.

• Knowledge of UVM verification methodologies.

• Practical experience with microprocessor designs.

• In-depth understanding of memory protection, translation, vector processing, and exception handling.

• Familiarity with constrained random stimulus, coverage types, checking methodologies, and behavioral models.

• Proficiency in C/C++.

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