Digital IC Design Engineer

A fast growing Semiconductor company seeks a talented and driven Digital IC Design Engineer. In this role, you’ll play a pivotal part in defining, designing, and verifying the digital components of a ground-breaking ASIC, working hand-in-hand with mixed-signal and digital design engineers.

Responsibilities

• Translate high-level specifications into intricate micro-architectures for the digital sub-blocks.
• Craft the digital sub-blocks using hardware description languages like Verilog or SystemVerilog.
• Develop comprehensive verification plans aligned with circuit specifications to ensure flawless operation.
• Establish Standard Delay Constraints (SDC) to guarantee proper timing behavior.
• Implement self-checking test benches for both individual blocks and the entire system, targeting both RTL and gate-level netlists.
• Collaborate with the measurement lab team to evaluate the fabricated ASIC and ensure it meets performance goals.
• Foster a collaborative and dynamic work environment to achieve the successful design of a next-generation ASIC.
• Actively participate in design reviews, offering valuable insights and fostering a culture of continuous improvement.
• Craft documentation that adheres to industry best practices for quality assurance.

Qualifications

• Master’s degree (MSc) or Doctorate (PhD) in Electrical Engineering or a comparable field, with 3+ years of hands-on experience in micro-architecture definition, RTL design, and verification.
• Strong foundation in digital electronics and signal processing principles.
• Proficiency in digital hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python).
• In-depth knowledge of SystemVerilog for advanced verification practices.
• Experience with the UVM verification methodology (a plus).
• Demonstrated analytical skills and the ability to solve complex problems effectively.
• Prior experience in designing and verifying digital functions for mixed-signal ICs is a plus.
• Familiarity with industry-standard RTL design flows (e.g., Cadence or Synopsys) is a plus.
• Team player with a critical eye for detail, a proactive approach, and excellent communication skills (written and verbal) in English.