Principal ASIC Design Engineer – Processor Sub-System

A leading semiconductor design company is looking for an experienced ASIC Design Engineer to join its team in Ottawa. The role will focus on cutting-edge processor sub-system design projects in networking technologies.

Responsibilities

• Translate high-level project requirements into detailed design specifications.
• Design micro-architecture for ASIC blocks and sub-systems.
• Develop and implement complex RTL logic (primarily using Verilog or System Verilog), and perform tasks such as block-level simulation, ASIC synthesis, and timing closure.
• Collaborate closely with verification, design, hardware, and support teams.
• Lead lab bring-up, product integration, and provide ongoing support.
• Offer technical guidance to customers, assisting them through intricate technical challenges.

Qualifications & Experience

• Bachelor’s degree in Electrical Engineering or equivalent experience.
• 15+ years of progressive, relevant experience in ASIC design.
• Expertise in modern ASIC development, including complex RTL design, synthesis, static timing analysis (STA), linting, logic equivalence checking (LEC), and a strong understanding of place and route (PnR).
• Proven experience with complex asynchronous clock boundaries and high-speed serial interfaces.
• Hands-on experience troubleshooting at the system level in a lab environment.
• Required knowledge in ARM Application Processor Sub-Systems, Processor Fabric Interfaces (coherent and non-coherent), Caches, and Non-Volatile Memory.
• Desirable expertise in Networking Switch/Router datapaths, Packet Processing, Optical Transport Network (OTN), and Ethernet.
• Familiarity with industry-standard interfaces such as 10/25/40/100Gb Ethernet, OTN, PCIe, SPI, I2C, USB, AXI, AHB, AMBA, GPIO, SRIO, DDR/SDRAM/DMA, and Non-Volatile Memory.
• Experience in test verification and scripting is a plus.
• Proven ability to work independently, collaboratively, and take on leadership roles.