Senior Timing Engineer

Senior Timing Engineer
As a leading technology innovator we push the boundaries of what’s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Engineers collaborate with cross-functional groups to determine product execution path.
What are we looking for?

• Extensive work experience in timing related activities and responsibilities such as library, LVF, AOCV/POCV/SOCV …etc
• Experience in CAD tools including correlation between different timing sign-off tools vs. Spice simulation across different metrics such as timing, noise, monte-carlo, etc
• Deep understanding of library characterisation process and flow with hands on experience on standard cell library characterisation
• Strong ability in automating and developing new flows to improve overall productivity of the team using Python, Perl, TCL, Bash … etc
• Working knowledge of Spice extraction, modelling and aging reliability model for latest technology nodes
• Proven knowledge of latest technologies nodes and practices in physical design including Place and Routs (P&R) and Static timing analysis (STA) sign-of
• Be willing to learn and involve in developing and validating new methodologies