Principal Verification Engineer (Memory)

Principal Verification Engineer (Memory) 
 
This company specialises in the creation of cutting-edge Intellectual Property (IP) that drives innovation across diverse high-tech industries. Join their team and contribute to the development of next-generation DDR memory controllers, powering a broad spectrum of advanced applications
 

Job Responsibilities:

• Architect and develop robust verification environments for complex IP, including Ethernet, CXL, and Storage, ensuring top-tier quality.
• Implement advanced UVM-SV scoreboards to automate self-checking regressions, guaranteeing thorough verification.
• Design and deploy comprehensive functional coverage strategies within Metric Driven Verification (MDV) environments, driving data-driven verification.
• Create and integrate SystemVerilog Assertions (SVA) for both formal and simulation environments, enhancing verification depth.
• Define and manage detailed verification plans (vPlans) using Cadence vManager, ensuring organized and efficient project execution.
• Establish and maintain automated regression environments using tools like Jenkins, maximizing testing efficiency.
• Actively participate in technical and checklist reviews as part of our ISO-9001 quality process, contributing to continuous improvement.
• Collaborate closely with design engineers to troubleshoot and resolve intricate test scenarios, fostering a strong team dynamic.
• Drive continuous improvement by enhancing quality, efficiency, and development processes through automation and innovative methodologies.
• Work seamlessly across diverse teams, including Design, Support, Delivery, Application Engineers, and the PHY team, promoting cross-functional collaboration.

Essential Requirements:

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering, Microelectronics, or a related field.
• 10-15 years of proven experience within the microelectronics/EDA industry.
• Extensive expertise in SystemVerilog Constrained Random Verification is mandatory.
• Deep understanding and practical application of Metric Driven Verification (MDV) are essential.
• Highly self-motivated with exceptional planning, interpersonal, and communication abilities.

Desirable Skills:

• Familiarity with front-end design tools for LINT, Synthesis, and CDC Analysis is a significant advantage.
• Experience with quality standards such as ISO-9001 and ISO-26262 is highly valued.
• Prior experience with AXI and/or CHI-E protocols is strongly preferred.