Senior ASIC Design Engineer – Sensors

Sensors-based hardware technology has a wide range of applications including navigation, gaming, smart user interface, multimedia, virtual reality and augmented reality. This challenging position offers the opportunity to work with leading edge sensor technologies embedded in smartphones, automotive, IOT, smartwatches as well as other consumer electronics devices. Job activities span the ASIC design process from specification definition, high-level design, coding and verification, RTL generation, and delivering a timing-closed netlist for layout. The successful candidate will work with architects of Systems, as well as other SoC team ASIC designers and software engineers to micro-architect and implement designs specific to Digital Sensor subsystems for integration into SoC for mobile applications.

Job responsibilities include:

• Architecting, designing and implementing digital sensor hardware for ASIC SoC
• Debugging, verifying, optimizing, and bit-exact matching with test vectors
• ASIC synthesis, static timing analysis and other post-RTL tools needed for delivering timing-closed designs for layout
• Power estimation and low-power design implementation
• Collaborating with Software Engineering and Systems Engineering Teams
• Adherence to Qualcomm’s processes for RTL and netlist releases
• Python automation, as well as enabling new methodologies, for improving workflows and team efficiency
• Participate in all project reviews
• Documentation

The position is technology focused and involves participation in a broad range of sensors systems engineering activities within the Sensors Technologies group

What are we looking for?

• Bachelor’s degree in Science, Engineering, or related field.
• RTL design, System Verilog, Tcl/Perl/Python shell-scripting skills
• 4+ years of RTL design experience on-chip with custom digital logic
• Experienced with ASIC RTL Synthesis, LEC, Power Extraction tools (PTPX), Primetime, RTL Linting tools and extensive usage of simulation tools.
• Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks is a plus
• Experience with C++/SystemC is a plus
• Familiarity with MBIST and DFT flow
• Gate level Simulation debug and usage of power extraction tools
• Strong analytical skills and ability to work in a dynamic and fast paced team environment
• Excellent written and verbal skills
• Strong interpersonal skills and a good team player
• Strong technical leadership and coaching skills