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Mixed-Signal Design Verification Engineer
Mixed-Signal Design Verification Engineer
About the Role:
Join a leading Mixed-Signal IP (MSIP) Design Verification team based in Cork, Ireland, working on advanced SoCs in cutting-edge technology nodes (3nm and below). This role involves verification of mixed-signal PHY IPs such as DDR, USB, PCIe, HDMI, DSI, CSI, and PLLs using the latest tools and methodologies.
Key Responsibilities:
- Perform SystemVerilog/UVM-based verification of SerDes, DDR, and PLL PHY IP
- Utilize both simulation and emulation techniques
- Collaborate closely with analog/digital design, architecture, software, and SoC teams
- Support integration of IPs into high-performance SoC platforms
- Contribute to post-silicon test, validation, and bring-up
Preferred Qualifications:
- Bachelor’s degree in Engineering, Computer Science, or related field
- Proficient in SystemVerilog/UVM and constrained-random verification
- Strong debugging skills and experience with coverage-driven verification
- Knowledge of low-power design and verification (UPF), GLS, and SDF flows
- Familiar with post-silicon test flows and automated test benches
- Scripting proficiency (Python, TCL, Perl, Shell)
- Experience in analog/mixed-signal verification is a plus
- Strong communication and teamwork abilities
Apply Now
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