ASIC Verification Engineer – 12 Month+ Contract

ASIC Verification Engineer – Contractor Role – 12 Months + Extensions 

Key Responsibilities:

• Define verification requirements and strategies for ASIC designs based on functional specifications and established development processes.

• Develop and implement verification environments and test cases to ensure thorough validation of design functionality.

• Monitor and drive functional and code coverage metrics to meet verification completion goals.

• Collaborate closely with design teams to debug RTL and resolve design issues efficiently.

• Work cross-functionally with development teams to align on product requirements and deliver optimized verification solutions.

• Contribute to the ongoing improvement of verification methodologies, tools, and internal processes.

• Produce clear and comprehensive documentation related to verification activities.

• Provide guidance and mentorship to junior engineers, fostering technical growth and best practices.

Qualifications:

• 5+ years of experience in ASIC verification.

• Master’s degree in Electrical or Computer Engineering or equivalent field.

• Strong proficiency in SystemVerilog and the UVM methodology.

• Experience with formal verification techniques.

• Knowledge of C, emulation platforms, and High-Level Synthesis (HLS) is a plus.

• Analytical mindset with a focus on results and timely delivery.

• Excellent written and verbal communication skills in English.

• Self-motivated, able to work independently, and collaborative in team environments.