3D Integration (Physical Implementation) Engineer

As a 3D Integration (Physical Implementation) Engineer, you will be at the forefront of advanced semiconductor design, focusing on the physical realization of high-performance multi-die systems.

Responsibilities

• Driving High-Speed Solutions: Develop cutting-edge, high-speed clock bus solutions and lead the technological evolution of inter-die and intra-die connections. Your work will directly contribute to achieving extreme Power, Performance, and Area (PPA) targets for our products.
• Advancing Multi-Die Physical Design: Conduct pioneering research and drive technological advancements in physical design methodologies for complex multi-die scenarios, including 2.5D and 3D integration (Chiplet, 3DIC). This encompasses:
  • Optimizing cross-die floorplanning, clock distribution, interconnects/buses, power delivery, and thermal management.
  • Developing and implementing robust cross-die physical design signoff methodologies.
  • Establishing and refining 3DIC reliability analysis methodologies.
• Leading Design Technology Co-Optimization: Spearhead or actively participate in end-to-end STCO (System-Technology Co-Optimization) and DTCO (Design-Technology Co-Optimization) initiatives, focusing on the development and evolution of physical design-related tools and methodologies.

Essential Requirements

• Expert in Physical Implementation: You must be proficient in back-end physical implementation, with extensive hands-on experience in high-speed physical design flows and tools. You should have a proven track record of participating in large-scale chip physical implementation and verification projects.
• Multi-Die Design Experience: Demonstrated experience in the planning or successful delivery of high-speed clock buses or advanced Chiplet/3DIC designs is crucial.
• Semiconductor Process Knowledge: Familiarity with the characteristics of mainstream semiconductor processes and strong process analysis capabilities are essential.
• Strategic & Technical Acumen: You can translate market requirements into actionable product planning and define overall chip architectures effectively.
• 3DIC System Mastery: Skilled in physical architecture planning, design, and signoff for complex Chiplet/3DIC systems.
• Education: Master’s degree or higher in Electronics, Communications, Computer Science, Mathematics, Automation, Materials Science, Physics, or a closely related field.
• Experience: 5–10 years of relevant experience in the semiconductor industry.