ASIC Design Architect – Display Interface

A leading semiconductor design company is seeking an experienced ASIC Design Architect or senior engineer to lead the development of IP for display interface technologies. This role offers the chance to contribute to an innovative and cutting-edge project in the automotive industry.

Responsibilities

• Architect and lead the design of new ASIC display interface IP for automotive applications.
• Translate high-level requirements into detailed technical specifications.
• Design, implement, and optimize RTL logic (primarily in Verilog or System Verilog), conduct block-level simulations, ASIC synthesis, DFT insertion, and timing closure.
• Collaborate with verification, design, emulation, and support teams to ensure seamless integration.
• Perform lab bring-up, product integration, and provide ongoing technical support.
• Serve as a technical leader, guiding customers through complex technical challenges.

Requirements
The ideal candidate will be a senior/staff/principal IC Design Engineer with the following qualifications:

• Bachelor’s degree (or equivalent experience) in Electrical Engineering or related field.
• 12+ years of relevant experience in ASIC design and development.
• Proven experience in architecting large ASIC sub-systems or complex digital IP.
• Expertise in modern ASIC development processes, including RTL logic design, physical synthesis, STA, lint, LEC, and a solid understanding of PnR.
• Proficiency in handling complex asynchronous clock boundaries and high-speed serial interfaces.
• Hands-on experience in lab environments, resolving issues at the system level.
• Experience with DisplayPort or DisplayPort Display Stream Compression (mandatory).
• Familiarity with HDMI or video over USB-C is a plus.
• Automotive semiconductor experience, including knowledge of functional safety and ISO 26262, is desirable.
• Experience with IC implementations of security features such as root of trust, key storage, authentication, encryption/decryption (AES GMAC/GCM) is highly desirable.
• ASIC verification experience using SystemVerilog/UVM is beneficial.
• Demonstrated ability to work independently, collaborate effectively, and lead teams.