ASIC Verification Engineer

Our client is a fast-growing Semiconductor start up. They are seeking an experienced ASIC Verification Engineer to join their team in developing cutting-edge digital designs. You will play a critical role in verifying complex SoC architectures, ensuring they meet rigorous functional, performance, and compliance standards. This is a hands-on role suited for someone with strong expertise in UVM-based environments and a passion for improving verification processes.

Responsibilities:

• Design, implement, and maintain UVM-based verification environments for advanced digital and SoC designs.
• Develop detailed verification plans and create targeted test cases based on functional specifications.
• Build and execute robust test benches to validate functionality, performance, and specification compliance.
• Proactively debug issues and collaborate closely with design teams to ensure timely resolution.
• Contribute to the evolution of verification methodologies, driving best practices and process improvements.
• Work cross-functionally to align verification activities with broader project goals and schedules.
• Participate in design and architecture reviews, offering insights from a verification standpoint.

Required Qualifications and Skills:

• Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
• 5+ years of experience in ASIC verification.
• Strong knowledge of digital logic design and verification techniques.
• Hands-on experience verifying processor-based systems.
• Proven track record in developing and deploying large SoCs on emulation platforms.
• Deep understanding of protocols such as PCIe, DDR, UCIe, and Ethernet.
• Proficiency in C/C++ and hardware verification languages (e.g., SystemVerilog, SystemC).
• Skilled in scripting languages such as Tcl, Perl, or Python.
• Expertise in at least one verification methodology (UVM, formal verification, or emulation).
• Full-cycle verification experience—from requirements gathering and planning to implementation, testing, and documentation.
• Familiarity with HW/SW co-simulation or emulation and tools like QEMU is advantageous, though not mandatory.