Back-End Technical Leader

Design Team seeks a highly motivated and experienced Back-End Technical Leader to spearhead the design and implementation of back-end components. You will play a key role in defining technical strategies, leading development processes, and ensuring product quality. Additionally, you’ll provide technical expertise to the Chief Product Officer and foster collaboration across teams.

Responsibilities

• Define, implement, and monitor back-end technical strategies.Lead methodology and design cycles for all physical partitions and top-level circuits.
• Oversee the evolution of development flows and stay updated on technological advancements.
• Champion effective hand-off procedures between back-end digital and front-end analog/layout teams.
• Ensure technical objectives are met, maintain product quality, and enforce proper documentation standards.
• Lead, organize, and participate in design reviews.
• Analyze customer feedback and translate it into actionable development plans.
• Design and implement multi-hierarchy, low-power physical designs.
• Utilize physical-aware logic synthesis, design for testability (DFT) techniques, floor planning, place and route, static timing analysis, IR drop analysis, and EM analysis for advanced technology nodes.
• Troubleshoot design and flow issues, propose solutions, and drive their execution.
• Deliver physical designs for end-to-end IPs or ASIC/SoC integrations.

Qualifications

• Bachelor’s degree in Electrical Engineering or equivalent experience.
• 10+ years of experience in physical design.
• Solid understanding of RTL-to-GDSII flow and design tape-outs for FDSOI and FinFET processes.
• Prior experience with low-power implementation techniques, including power gating, multiple voltage rails, and UPF/CPF knowledge.
• Proven experience working with EDA tools like DC/Genus, ICC2/Innovus, PrimeTime, Redhawk/Voltus, and Calibre.
• Experience running physical-aware logic synthesis and achieving optimal QoR on low-power designs.
• Knowledge of static timing analysis concepts, defining timing constraints, and corner/voltage definitions.
• Experience with block-level and full-chip floor planning (ideally with IOs bumps) and power grid planning.
• Experience with custom or regular clock tree synthesis at block or top level, and clock power reduction techniques.
• Proficiency in scripting languages like Python, TCL, or Perl.