DTCO Engineer (Design Technology Co-Optimization)

Join a global leader in information and communications technology (ICT) infrastructure and smart devices. A privately held company dedicated to bringing digital to every person, home, and organization for a fully connected, intelligent world.

Responsibilities

• Driving Advanced Process Optimization: Lead DTCO efforts for cutting-edge process nodes, collaborating closely with our Fab, design, and product teams. You’ll define technology roadmaps, pinpoint optimization opportunities, enhance manufacturing processes, and significantly boost Power, Performance, and Area (PPA).
• Defining & Mitigating Risks: Define and fine-tune process “knobs,” proactively identifying potential process and design risks. You’ll then develop and propose effective mitigation or optimization strategies to ensure robust designs.
• Optimizing Device & Architecture: Based on ambitious PPA targets, you’ll define device types and specifications, and strategically optimize standard cell and SRAM architectures. This includes delivering precise Design Rule Manual (DRM) requirements.
• Enhancing Manufacturability & Reliability: Analyze and address process and design risks from Optical Proximity Correction (OPC), Design for Manufacturability (DFM), and Design for Reliability (DFR) perspectives, proposing crucial improvements.
• Strategic SoC-Level Optimization: Leverage module-level physical design PPA analysis to propose comprehensive SoC-level optimization strategies. This will encompass refining physical design flows, optimizing Power Delivery Network (PDN) designs, and defining optimal metal stacks.
• PPA Benchmarking & Analysis: Develop robust benchmarking methodologies to accurately analyze and interpret PPA data, providing critical insights for decision-making.
• Leading Industry Trends: Conduct in-depth research on industry DTCO trends and competitive landscapes. You’ll help steer our DTCO direction and define competitive process platforms.

Essential Requirements

• DTCO Expertise: You possess an in-depth understanding of Design-Technology Co-Optimization principles and applications.
• Broad Semiconductor Experience: Demonstrated experience across various aspects of semiconductor development, including process integration, OPC, DFM, circuit design, integrated circuit design, FIP (e.g., standard cell and SRAM) design, device and model definition, and Design Rule Manual (DRM) development.
• Foundational Knowledge: Familiarity with semiconductor process flows, product development cycles, ground rules, IC design, circuit analysis, layout, RC extraction, and Place and Route (P&R).
• Tool & Debugging Proficiency: Proficient in using Process Design Kits (PDKs), circuit design/simulation, layout, and Design Methodology tools. You have a strong ability to debug and resolve complex technical issues.
• PPA Benchmarking Acumen: Solid knowledge of technology PPA (Power, Performance, Area) benchmarking techniques.
• Education: Master’s degree or higher in Microelectronics, Electronics, Electrical Engineering, Materials Science, Physics, or a closely related field.
• Experience: 5–10 years of relevant experience in the semiconductor industry.