GPU CAD Flow Methodology Engineer

Recruitment Consultant

Liam Geary

Contact Details

[email protected] +44 (0)330 335 2402

Posted

1 month ago

This is a GPU ASICS position ideally for a Senior or Staff level Engineer

Responsibilities

RTL to GDS2 flow, tools and methodologies such as synthesis, static timing analysis, formal verification, physical design and ECO generation/verification :
Implementation and delivery of GPU cores from RTL to GDSII
Identify areas for flow and process improvements
RTL synthesis using physically aware tools
Formal Verification using industry standard tools for RTL-netlist and netlist-netlist checks
Close design timing by running static timing analysis and constraint development
Generate and verify ECOs for functional and timing fixes, working closely with the physical design team
Low Power synthesis flows for multiple corners
Synthesis, static timing, timing closure, constraints and formal verification
EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime
EDA tools for synthesis, logic equivalence checking, timing Analysis, physical design
Able to problem solve complex, unique and detailed issues
Experience in Synthesis or Physical Design Flows, CAD tool development
Develop complex SW for design implementation in Python, Perl, Shell and Tcl

What are we looking for?

Synthesis
Place and Route
Static timing analysis
Clocking
Power Grid architecture
High performance designs.

Industry

Semiconductor

Contract Type

Permanent

Location

Ireland

Work Model

On-Site

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