RTL Design Engineer – FPGA/ASIC

Recruitment Consultant

Jamie Coltman

Contact Details

jc@eu-recruit.com +44 (0)333 307 1115

Posted

2 days ago

Our client is a fast-growing Semiconductor start-up, who are seeking a highly skilled RTL Design Engineer with experience in FPGA and/or ASIC development to join their team. This role involves designing and implementing high-performance digital systems, collaborating with cross-functional teams, and contributing to cutting-edge hardware solutions.

Responsibilities:

Develop RTL designs for FPGA and ASIC applications using Verilog (or VHDL).
Translate system-level specifications into efficient, scalable digital architectures.
Optimize designs for timing, power, and area through synthesis and place-and-route using tools like Xilinx Vivado.
Ensure design closure and compliance with performance constraints via detailed post-synthesis and post-route analysis.
Apply RTL design best practices including modular design, code reuse, and pipelining techniques.
Collaborate closely with hardware, software, and system engineering teams to define and integrate FPGA/ASIC requirements.
Maintain clear and comprehensive documentation for RTL designs, specifications, and user guides.
Provide project updates, monitor progress against milestones, and proactively highlight risks or issues.
Stay abreast of industry trends, tools, and technologies in FPGA/ASIC development and evaluate new solutions for ongoing and future projects.
UVM experience is a plus.

Required Qualifications:

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field (Master’s degree preferred).
Minimum 5 years of hands-on experience in RTL design and coding.
Proficiency in Verilog and strong understanding of digital design fundamentals.
Demonstrated experience with FPGA and ASIC development workflows.
Familiarity with Xilinx, Intel/Altera FPGA platforms.
Strong grasp of digital logic design, finite state machines, and SoC architecture.
Experience with synthesis, timing closure, and physical design constraints.
Background in developing high-performance or real-time FPGA-based systems.
Experience with SoC design is highly desirable.

Industry

Semiconductor

Contract Type

Permanent

Location

Netherlands

City

Amsterdam

Work Model

On-Site

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RTL Design Engineer – FPGA/ASIC

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