Senior ASIC Design Engineer

Based in Ottawa, our client is a prominent figure in the Canadian electronic design community, specializing in ASIC and FPGA design and verification, as well as embedded software development services. They excel in bolstering their clients’ teams and expediting the development of comprehensive designs.

With adaptability and efficiency as their hallmarks, their workforce comprises exceptional individuals committed to excellence. Their relentless pursuit of mastery in their field propels their ongoing success and expansion. Presently, they are actively seeking several pivotal technical resources, including a Staff or Principal ASIC Design Engineer.

Key Responsibilities

• Interpret high-level requirements and transform them into meticulous specifications.
• Design and execute RTL logic (predominantly Verilog or System Verilog), conduct block-level simulation, ASIC synthesis, DFT insertion, and ensure timing closure.
• Collaborate closely with the verification team, design team, hardware team, and support team.
• Conduct lab bring-up, facilitate product integration, and provide support.
• Deliver technical assistance to clients, guiding them through intricate technical challenges.

Key Qualifications

We seek a seasoned individual, preferably a senior/staff/principal IC Design Engineer, possessing the following attributes:

• Bachelor’s degree in electrical engineering or equivalent skills/experience.
• Over 8 years of relevant experience in progressively senior roles.
• Knowledge of high-speed compute (e.g. floating-point vector processing units (VPU), GPU shader hardware or similar floating point ALUs), embedded SRAM controllers, ARM/MIPS/RISC-V Architecture (Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation, etc.) and/or familiarity with AMBA/APB/AXI and processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C etc
• Experience integrating 3rd party PCIE controller + Serdes, HBM controller +PHY. 
• Experience with timing closure at high frequencies, along with familiarity with low power UPF flow, for defining power intent of chips with multiple power domains.