Senior ASIC Verification Engineer

Our client is a leading provider of electronic design services, specializing in ASIC and FPGA design and verification, as well as embedded software development. Serving the Canadian design community, we enhance and support their clients’ teams to accelerate the completion of comprehensive designs.

Their adaptable and efficient approach, combined with a highly talented staff, drives their aim to be industry leaders. Due to their ongoing success and growth, they are seeking highly skilled technical professionals worldwide, including a Senior ASIC Verification Engineer with extensive expertise in UVM and SystemVerilog.

As a Senior ASIC Verification Engineer, you will utilize SystemVerilog and UVM to perform constrained random functional coverage-based verification. You will work from specification to coverage-closed verified and debugged designs, developing verification environments, and leveraging third-party VIP as needed. You will be responsible for verifying blocks, sub-systems, or top-level components within complex networking or GPU/AI SoCs in advanced technology nodes, including down to 3nm FinFET. You will collaborate with a highly experienced team on world-class ASIC environments.

Responsibilities

• Lead verification activities for blocks or entire chips.
• Develop verification environment architecture using UVM.
• Document test environment associations and write test cases.
• Apply constrained random verification methods.
• Support lab bring-up with direct test cases.
• Perform code and functional coverage analysis.

Qualifications

• 8+ years of experience in ASIC verification.
• Proficiency in Verilog, SystemVerilog, other hardware description languages, and scripting languages.
• Extensive experience with OVM/UVM methodologies.
• Strong understanding of constrained random verification techniques, assertions, and functional coverage.
• Experience with SONET, OTN, Ethernet, PCIe is a significant asset.
• Excellent interpersonal and communication skills; a team player.