Senior Digital ASIC Design Engieer

Senior Digital ASIC Design Engineer 

The Role

Technically hands on role working in a fast paced start-up environment with a cutting-edge company developing ultra-energy efficient chips. 

Experience

• Strong understanding of digital design architectures and implementation of DSP algorithms
• RTL design with VHDL/Verilog/SystemVerilog
• Strong experience/background of RTL-to-GDSII flow with Cadence tools
• Strong understanding of design I/O constraining at the Analog/Mixed Signal interface (most important)
• Knowledge of digital verification
• Hands-on experience on timing-closure techniques
• Preferably experience with clock domain crossing solutions