Senior SerDes System Engineer

Senior SerDes System Engineer – Signal Integrity

Responsibilities

• Lead innovation in high-speed (112Gbps+) interconnection technology for ICT products
• Architect and design high-speed SerDes systems, conduct simulations
• Validate high-speed SerDes systems experimentally and correlate results with simulations
• Collaborate with the team in China, including technical reviews, regular reporting, and project planning
• Develop technology roadmaps and plan projects for high-speed interconnections, providing technical insights into high-speed systems

Job Requirements

• Master’s degree or higher, with a preference for a PhD in Electrical Engineering, Information Technology, Communication Engineering, Electromagnetic Science, etc. More than 8 years of work experience
• Extensive knowledge and experience in hardware architecture design for telecom/communication products
• Extensive experience in developing high-speed (56Gbps and beyond) products/prototypes and successfully delivering them
• Excellent understanding of high-speed SerDes architecture, including Rx/Tx SerDes PHY, Tx/Rx equalization techniques, CDR, and challenges at the DSP level
• Familiarity with key high-speed serial hardware such as SerDes, high-speed ASICs, packages, DSPs, PCBs, and connectors
• Proficiency in conducting high-speed serial links lab experiments/prototyping (using real-time oscilloscopes, VNA, etc.) and correlating results with simulations
• Knowledge of industry standards such as IEEE 802.3/OIF-CEI, Common Electrical I/O (CEI)-224G, or InfiniBand
• Academic background with a willingness to participate in conferences and industry events
• Enthusiasm for technology, with curiosity, ability, and motivation to make significant contributions in the field

Job Tools / Technical Work

• High-speed SerDes modeling and simulation using Python (preferred), Matlab, Verilog-A, ADS
• Signal integrity tools: HFSS, CST