Senior STA CAD Engineer

ID: 3071937

The Global CAD team defines and enables the RTL to GDSII flows for variety of advanced low power and high performance SOCs, enabling state-of-the-art chipsets from Qualcomm.

The Design Flow Development team is looking for outstanding engineers with experience in STA, timing ECO and PDN methodology. The candidate will drive best-in-class sign-off flows for >1billion device SOCs in cutting edge technologies.

The candidate will be responsible for:

The engineer will be member of team developing chip STA methodology and flow:

– STA  and timing ECO technologies, design closure methodology with unique challenges driven by Low power architecture, Si Variation, Low voltage operation and other challenges.

– Constraints clean up and correlation, multi-voltage analysis, overall STA flow development,

– Timing methodologies for large SoC signoff and derating & margin mechanism

– CAD automation for timing data mining and processing

– Participating in project proposal development including key milestones and deliverables

– Execute and deliver project goals in a timely manner with production support

– Resolve issues in all phases of development to assure smooth project execution

We would love to see:

• Expertise in Primetime, Primeshield and Tempus based, hierarchical analysis for large SoCs
• Hands on Tweaker, Tempus ECO and PTECO for timing closure
• Highly Proficient in Python, TCL and Perl
• Interest in Design for Parametric Yield is an added advantage.
• Comfortable with extraction, simulation tools and environments is a plus
• Excellent problem-solving skills and results-driven, able to work and drive practical solutions under research environment.
• Good communication skill and personal skills in a multi-disciplinary, fast-paced engineering environment
• Minimum Qualification Master’s of Computer Engineering or Electrical Engineering
• 4+ years industrial work experience.