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Analog Layout Engineer

Recruitment Consultant
Chris Canneaux
Posted
1 month ago

We are actively seeking a resourceful Analog Layout Engineer, based in either Reading, UK or Lausanne, Switzerland.

 

Responsibilities

  • Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes
  • Layout and verification of very high-speed analog circuits
  • Interact closely with the design team to understand requirements and implement solutions
  • Support IP and chip level integration
  • Support and interact with customers on requirements, and IP delivery
  • Exposure to flip-chip package technologies

 

Experience

  • Experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits
  • Expertise in layout of high-speed/frequency circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc.
  • Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements
  • Ideally with experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
  • User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc.
Industry
Semiconductor
Contract Type
Permanent
Location
Switzerland
Work Model
On-Site

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