Senior Digital Verification Engineer

Recruitment Consultant

Chris Canneaux

Contact Details

[email protected] +44 (0)330 335 2350

Posted

6 days ago

A growing Semiconductor Manufacturer are seeking a Senior Digital Verification Engineer to lead the development of the digital verification framework and infrastructure for complex digital and mixed-signal ICs. This role involves working with cutting-edge technologies and industry-standard ASIC tools to design and verify products such as power management, signal management, and mixed-signal functions.

Responsibilities

Define and develop a UVM and System Verilog based digital verification environment.
Standardize, define, develop, and document Verification IPs (VIPs).
Integrate VIPs into the project’s digital verification environment.
Define digital verification metrics for RTL and gate-level verification.
Develop test plans and implement them.
Automate digital verification processes and scripting.
Develop and manage regression infrastructure.
Collaborate closely with senior digital and analog designers to develop VIP models.
Review digital verification metrics and results from multiple projects.
Define and design top-level digital verification tests.
Analyze and debug test results, code coverage, and functional coverage.
Estimate, plan, and schedule digital verification tasks to meet tape-out dates.

Qualifications

PhD, BS, or MS in Electrical Engineering with a focus on Digital Design or VLSI coursework.
5+ years of extensive experience in RTL and gate-level verification.
Proficiency in digital verification languages and standards, particularly UVM and System Verilog.
Advanced skills in constraint random tests, SV assertions, coverage metrics, analog and digital DV modeling, DV test plans, regression analysis, and UVM DV agents (Monitor, Driver, Scoreboard).
Comprehensive knowledge and experience throughout the entire digital design flow, including specification definition, RTL verification, synthesis, P&R, gate-level verification, power estimation, ATPG generation and simulation, and AMS simulations.
Proficient in using industry-standard ASIC tools and flows, including digital simulators, synthesis tools, DFT, LEC, and STA.
Strong scripting and automation skills in TCL, Python, or C/C++.
Leadership skills to guide the digital verification team and mentor junior designers.
Excellent written and verbal communication skills, and a strong team player.

Industry

Semiconductor

Contract Type

Permanent

Location

Germany

Work Model

On-Site

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