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Verification Engineer (Contract)

Recruitment Consultant
Joseph Hughes
Posted
2 months ago

This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the hardworking System IP team!
 This is a fast-paced technical role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of our Systems!
 

Responsibilities

  • Reviewing and assessing proposed design changes from a verification complexity point of view
  • Ownership of verification environment from investigation all the way to verification closure
  • Develop, extend, maintain, and improve our SVA Formal testbenches
  • Develop, extend, maintain and improve our suite of SVA Protocol Checkers for Formal and Simulation use
  • There will be opportunities for improving our verification methodology and mentoring other members of the team
  • Close collaboration with other engineering teams leading to high quality IP that works well in a complete system.

 

Requirements

  • Experience of architecting and implementing formal verification environments for complex IP/module level designs.
  • Experience of property-based model-checking or Formal Property verification
  • Practical experience of writing assertions using SystemVerilog Assertions (SVA) with an industry leading formal tool (e.g. Cadence, Mentor, Synopsys tools).
  • Team leadership and mentoring experience
  • Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI)
     
Industry
Semiconductor
Contract Type
Contract
Location
United Kingdom
Work Model
On-Site

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