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range of industries within the field of technology
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Performance Modelling Engineer
Performance Modelling Engineer
Location: Cambridge, UK
Type: Contractor
Headcount: 2
Experience: 4+ years
Visa: Visa sponsorship is not available for this contractor position.
About the Role
Our client is looking for Performance Modelling Engineers to join a CPU Architecture team working on next-generation processor technologies.
You will use modelling, simulation and workload-characterisation techniques to evaluate potential CPU hardware designs and provide data-driven insights that influence future architectural features.
Key Responsibilities
- Design, implement and improve performance models for CPU microarchitectures.
- Maintain and develop cycle-accurate, trace-driven and statistical simulation environments.
- Analyse the performance and power implications of proposed CPU features.
- Conduct architectural trade-off and cost-benefit analysis.
- Develop methodologies and automated workflows for performance analysis.
- Create visualisations and analytical tools to identify CPU performance bottlenecks.
- Collaborate with CPU architects, software engineers and performance modelling specialists.
Requirements
- Bachelor’s or Master’s degree in Computer Science, Electrical Engineering or a related discipline.
- 4+ years of relevant industry experience.
- Hands-on experience in CPU performance modelling and microarchitecture analysis.
- Familiarity with cycle-accurate, cycle-approximate or functional simulators.
- Understanding of CPU pipelines and common architectural performance metrics.
- Strong C/C++ development skills.
- Working knowledge of Python for scripting and data analysis.
- Strong analytical, communication and collaboration skills.
Desirable
- Experience with CPU power models and cache-system models.
- Strong software engineering background covering design, coding, testing and debugging.
- Knowledge of Arm architectures such as Armv8-A or Armv9-A.
- Experience with microarchitecture performance counters.
- Hardware/software co-optimisation experience.
- Exposure to RTL or SystemC simulation.
- Broader system architecture or system software knowledge.
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