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RF/Analog ASIC Layout Engineer
Mixed Signal ASIC Layout Engineer
Description
We are looking for an experienced Mixed Signal ASIC Layout Engineer with strong expertise in RF/Analog physical design for SiGe BiCMOS technologies. The role focuses on custom layout design, verification, and tape-out of RF/analog circuit modules, working closely with RF IC design and RF system teams in a highly specialized, on-site engineering environment.
Sectors
Semiconductor & ASIC Design
RF / Analog Integrated Circuits
SiGe BiCMOS Technologies
High-Frequency & Mixed-Signal Systems
Company Size & Type
Technology-driven semiconductor and electronics organization
Highly specialized R&D environment
Strong collaboration between layout, design, and system engineering teams
Focus on high-performance, RF-centric IC development
Non-Negotiable Requirements (Must Have)
Completed degree in Electrical Engineering or a comparable technical field
Several years of professional experience in custom RF/analog ASIC layout
Extensive hands-on experience with SiGe BiCMOS processes
Strong proficiency in Cadence Virtuoso XL for physical design
Deep understanding of full custom layout flows, from schematic to GDSII
Proven experience with physical verification, including:
DRC
LVS
Tools such as Cadence Assura / PVS
Detailed knowledge of layout techniques for:
Device matching
Parasitic reduction
RF shielding
High-frequency routing
Experience with floor-planning in close collaboration with RF IC design and RF system teams
Experience executing tape-out procedures
Good communication skills and ability to work closely with interdisciplinary teams
Negotiation-level German and basic English language skills
Suitable for experienced professionals (not a role for career starters)
Desirable Requirements (Nice to Have)
Experience scripting and automating layout tasks using SKILL and/or Python
Familiarity with advanced process design kits (PDKs) and foundry interfaces
Experience working in high-frequency or RF system-level projects
Strong attention to detail and quality in layout verification and sign-off processes
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