Senior Timing Engineer

Recruitment Consultant

Liam Geary

Contact Details

lg@eu-recruit.com +44 (0)330 335 2402

Posted

27 days ago

Sr Timing Engineer
As a leading technology innovator, we push the boundaries of what’s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Engineers collaborate with cross-functional groups to determine product execution path.
What are we looking for?
•
Extensive work experience in timing related activities and responsibilities such as library, LVF, AOCV/POCV/SOCV …etc
•
Experience in CAD tools including correlation between different timing sign-off tools vs. Spice simulation across different metrics such as timing, noise, monte-carlo, etc
•
Deep understanding of library characterisation process and flow with hands on experience on standard cell library characterisation
•
Strong ability in automating and developing new flows to improve overall productivity of the team using Python, Perl, TCL, Bash … etc
•
Working knowledge of Spice extraction, modelling and aging reliability model for latest technology nodes
•
Proven knowledge of latest technologies nodes and practices in physical design including Place and Routs (P&R) and Static timing analysis (STA) sign-of
•
Be willing to learn and involve in developing and validating new methodologies
Preferred Qualifications:
•
Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
•
3+ years of ASIC design, verification, validation, integration, or related work experience.
•
2+ years of experience with architecture and design tools.
•
2+ years of experience with scripting tools and programming languages.
•
2+ years of experience with design verification methods.
Principal Duties & Responsibilities:
•
Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
•
Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
•
Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.
•
Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
•
Utilises tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.
•
Writes detailed technical documentation for EDA/IP/ASIC projects

Industry

Semiconductor

Contract Type

Permanent

Location

Ireland

City

Cork

Work Model

On-Site

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