Digital Physical Design Engineer

Recruitment Consultant

Chris Canneaux

Contact Details

ccanneaux@eu-recruit.com +44 (0)330 335 2350

Posted

1 month ago

Physical Design Engineer, Digital

Location: Munich
In office presence: 2-3 days / week

As a contractor, you will participate in the physical implementation flow for complete MCU SoCs. Your responsibilities will include:

Performing RTL-to-gate synthesis based on MCU-specific requirements
Creating and refining timing constraints
Reviewing constraints with the front-end team and proposing RTL improvements for timing critical paths
Running Static Timing Analysis (STA) and closing timing
Implementing and analyzing clock trees
Optimizing the design for low-power targets
Supporting floorplanning and physical distribution of components in the SoC floorplan
Performing routing, signal integrity checks, IR drop analysis, and implementing fixes
Selecting technology libraries and transforming RTL functionality into structural components
Contributing to physical verification of timing, power, and overall design quality
Writing scripts (TCL/Perl/Python) to automate and optimize the physical design flow

Required Skills & Experience

Hands-on experience with the Cadence Physical Design Flow
Strong expertise in the following areas:
- RTL-to-Gate synthesis
- Timing-constraint development
- STA and timing closure
- Clock-tree implementation
- Low-power optimization
- Floorplanning and manual layout
- Signal-integrity and IR-drop analysis
- Scripting skills in TCL, Perl, or Python
- Experience working in a UNIX/Linux environment

Industry

Semiconductor

Contract Type

Contract

Location

Germany

City

Munich

Work Model

On-Site

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