Principal CPU Microarchitect

Principal CPU Microarchitect

Position Overview

A leading semiconductor and computing research organization is seeking a Principal CPU Microarchitect to contribute to the development of next-generation out-of-order processor cores for advanced mobile and compute platforms.

This role focuses on CPU microarchitecture innovation, architecture modeling, and workload-driven optimization. The successful candidate will work on defining and evaluating microarchitectural features across the processor pipeline, leveraging cycle-accurate simulation and deep workload analysis to drive performance, efficiency, and scalability improvements.

The position involves close collaboration with compiler, runtime, and hardware implementation teams to shape future CPU architectures.

Key Responsibilities

CPU Microarchitecture Design

• Define and specify microarchitectural enhancements across:
  • Front-end fetch and decode stages
  • Out-of-order execution engines
  • Load/store subsystems
  • Branch prediction mechanisms
  • Prefetching systems
  • Cache and memory hierarchy
• Evaluate architectural trade-offs for performance, power, and scalability.

Architecture Modeling & Performance Evaluation

• Develop and maintain cycle-accurate processor models using simulators such as gem5 or equivalent frameworks.
• Evaluate new architectural features using industry-standard benchmarks and representative real-world workloads.
• Conduct detailed workload analysis to identify bottlenecks and quantify optimization opportunities.

Performance Analysis & Optimization

• Use profiling methodologies including:
  • Hardware performance counters
  • Trace-based analysis
  • Top-down performance analysis
• Investigate and optimize behavior across compute, memory, and execution subsystems.
• Drive workload-aware architectural innovation for modern applications.

ISA & System Co-Design

• Collaborate with compiler and runtime teams on ISA and system-level enhancements.
• Contribute to:
  • ISA extension design
  • Prefetching hints and semantic acceleration mechanisms
  • Runtime-aware architectural optimizations
• Support hardware/software co-design initiatives.

Technical Leadership & Collaboration

• Author detailed architecture and microarchitecture specifications.
• Work closely with downstream implementation and design teams to guide feature realization.
• Mentor junior engineers and contribute to broader technical strategy and innovation initiatives.

Required Qualifications

• MSc or PhD in Computer Science, Electrical Engineering, or related field.
• Strong hands-on experience with CPU microarchitecture, particularly out-of-order processors.
• Deep expertise in at least one major architecture domain, such as:
  • Branch prediction
  • Prefetching
  • Out-of-order execution
  • Memory hierarchy
  • Cache coherence systems
• Experience with cycle-accurate simulators (e.g., gem5 or proprietary tools).
• Strong workload analysis and performance profiling experience.
• Proficiency in:
  • C++
  • Python
• Familiarity with modern ISA architectures such as:
  • ARM
  • x86_64
  • RISC-V

Preferred Qualifications

• PhD in Computer Architecture or related discipline.
• Publications in leading architecture conferences.
• Experience with:
  • Dynamic language runtimes and JIT/AOT compilation
  • AI/ML inference optimization on CPUs
  • CPU–accelerator co-design
• Track record of architectural features delivered into production silicon.
• Familiarity with AI-assisted design exploration and automated optimization workflows.

Personal Attributes

• Strong analytical and systems-level thinking capabilities.
• Deep curiosity for modern processor architecture and performance optimization.
• Ability to bridge architectural research and practical silicon implementation.
• Strong communication and collaboration skills across multidisciplinary teams.
• Mentorship mindset with ability to guide technical direction.