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At European Recruitment, our sectors cover a wide
range of industries within the field of technology
At European Recruitment, our sectors cover a wide
range of industries within the field of technology
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At European Recruitment, our sectors cover a wide range of industries within the field of technology
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At European Recruitment, our sectors cover a wide range of industries within the field of technology
Senior Physical Design Engineer
We are looking for a Senior Physical Design Engineer to join a growing engineering team in Ottawa. In this role you would take ownership of backend implementation from netlist through to GDSII across challenging ASIC blocks and sub-systems.
You will work with advanced physical design flows and single-digit FinFET technology nodes, collaborating with an experienced engineering team to deliver complex designs through to successful closure.
This is a fully remote senior-level position, open to candidates based anywhere.
Key Responsibilities
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Own place & route implementation and analyze physical design results.
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Develop effective floorplans to support physically-aware synthesis.
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Drive designs through timing closure and physical verification.
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Debug issues across EDA tools, timing constraints, DFT, and RTL/design implementation.
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Work closely with front-end design teams to improve RTL quality and implementation efficiency.
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Implement timing ECOs and optimize designs for performance.
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Run PrimeTime and analyze timing reports.
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Develop strategies to optimize power, performance, and area (PPA).
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Perform IR-drop analysis and implement optimization strategies.
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Collaborate with analog, front-end, and other physical design teams to align implementation objectives.
Key Qualifications
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8+ years of experience in ASIC digital physical design / place & route.
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Strong hands-on experience with leading Synopsys and Cadence EDA tools and flows.
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Experience working with advanced FinFET technology nodes, including DRC rules and node-specific P&R requirements.
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Strong practical experience in floorplanning and physical implementation.
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Solid understanding of Clock Tree Synthesis (CTS) and clock design for timing closure.
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Experience with IR-drop analysis and optimization.
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Strong background in timing closure and ECO implementation; PT-ECO or Tweaker experience is a plus.
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Strong scripting and automation skills.
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Experience with several of the following: synthesis, StarRC, PrimeTime DMSA, RedHawk, Calibre, LEC, or Formality.
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A self-motivated, proactive approach with the ability to work effectively both independently and as part of a collaborative engineering team.
Apply Now
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